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3.3v zero delay buffer cy2308 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07146 rev. *b revised december 14, 2002 8 features zero input-output propagation delay, adjustable by capacitive load on fbk input multiple configurations, see ?available cy2308 configurations? table multiple low-skew outputs ? output-output skew less than 200 ps ? device-device skew less than 700 ps ? two banks of four outputs, three-stateable by two select inputs 10-mhz to 133-mhz operating range low jitter, less than 200 ps cycle-cycle ( ? 1, ? 1h, ? 4, ? 5h) space-saving 16-pin 150-mil soic package or 16-pin tssop 3.3v operation industrial temperature available functional description the cy2308 is a 3.3v zero delay buffer designed to distribute high-speed clocks in pc, workstation, datacom, telecom, and other high-performance applications. the part has an on-chip pll which locks to an input clock presented on the ref pin. the pll feedback is required to be driven into the fbk pin, and can be obtained from one of the outputs. the input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps. the cy2308 has two banks of four outputs each, which can be controlled by the select inputs as shown in the table ? se- lected input decoding. ? if all output clocks are not required, bank b can be three-stated. the select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. the cy2308 pll enters a power down state when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off, resulting in less than 50 a of current draw. the pll shuts down in two additional cases as shown in the ? select input decoding ? table. multiple cy2308 devices can accept the same input clock and distribute it in a system. in this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. the cy2308 is available in five different configurations, as shown in the ? available cy2308 configurations ? table on page 2 . the cy2308 ? 1 is the base part, where the output frequen- cies equal the reference if there is no counter in the feedback path. the cy2308 ? 1h is the high-drive version of the ? 1, and rise and fall times on this device are much faster. the cy2308 ? 2 allows the user to obtain 2x and 1x frequen- cies on each output bank. the exact configuration and output frequencies depends on which output drives the feedback pin. the cy2308 ? 3 allows the user to obtain 4x and 2x frequen- cies on the outputs. the cy2308 ? 4 enables the user to obtain 2x clocks on all outputs. thus, the part is extremely versatile, and can be used in a variety of applications. the cy2308 ? 5h is a high-drive version with ref/2 on both banks. 9 16 fbk clka4 clka3 v dd gnd clkb4 clkb3 s1 block diagram 1 2 3 4 5 6 7 8 10 11 12 13 14 15 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 soic top view pin configuration ref clka1 clka2 clka3 clka4 fbk pll mux select input decoding s2 s1 clkb1 clkb2 clkb3 clkb4 /2 extra divider ( ? 2, ? 3) /2 extra divider ( ? 3, ? 4) extra divider ( ? 5h) /2
cy2308 document #: 38-07146 rev. *b page 2 of 13 notes: 1. outputs inverted on 2308 ? 2 and 2308 ? 3 in bypass mode, s2 = 1 and s1 = 0. 2. output phase is indeterminant (0 or 180 from input clock). if phase integrity is required, use the cy2308 ? 2. 3. weak pull-down. 4. weak pull-down on all outputs. 5. weak pull-ups on these inputs. pin description pin signal description 1ref [3] input reference frequency, 5v tolerant input 2 clka1 [4] clock output, bank a 3 clka2 [4] clock output, bank a 4v dd 3.3v supply 5 gnd ground 6 clkb1 [4] clock output, bank b 7 clkb2 [4] clock output, bank b 8s2 [5] select input, bit 2 9s1 [5] select input, bit 1 10 clkb3 [4] clock output, bank b 11 clkb4 [4] clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 [4] clock output, bank a 15 clka4 [4] clock output, bank a 16 fbk pll feedback input select input decoding s2 s1 clock a1 ? a4 clock b1 ? b4 output source pll shutdown 0 0 three-state three-state pll y 0 1 driven three-state pll n 10 driven [1] driven [1] reference y 11 driven driven pll n available cy2308 configurations device feedback from bank a frequency bank b frequency cy2308 ? 1 bank a or bank b reference reference cy2308 ? 1h bank a or bank b reference reference cy2308 ? 2 bank a reference reference/2 cy2308 ? 2 bank b 2 x reference reference cy2308 ? 3 bank a 2 x reference reference or reference [2] cy2308 ? 3 bank b 4 x reference 2 x reference cy2308 ? 4 bank a or bank b 2 x reference 2 x reference cy2308 ? 5h bank a or bank b reference /2 reference /2
cy2308 document #: 38-07146 rev. *b page 3 of 13 zero delay and skew control to close the feedback loop of the cy2308, the fbk pin can be driven from any of the eight available output pins. the output driving the fbk pin will be driving a total load of 7 pf plus any additional load that it drives. the relative loading of this output (with respect to the remaining outputs) can adjust the input- output delay. this is shown in the graph above. for applications requiring zero input-output delay, all outputs including the one providing feedback should be equally load- ed. if input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. for zero output-output skew, be sure to load outputs equally. for further information on using cy2308, refer to the applica- tion note ? cy2308: zero delay buffer. ? maximum ratings supply voltage to ground potential................ ? 0.5v to +7.0v dc input voltage (except ref) ............... ? 0.5v to v dd + 0.5v dc input voltage ref............................................ ? 0.5 to 7v storage temperature................................. ? 65 c to +150 c junction temperature...................................................150 c static discharge voltage (per mil-std-883, method 3015)............................. >2000v ref. input to clka/clkb delay v/s difference in loading between fbk pin and clka/clkb pins operating conditions for cy2308sc-xx commercial temperature devices parameter description min. max. unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance, below 100 mhz 30 pf load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance [6] 7pf t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms
cy2308 document #: 38-07146 rev. *b page 4 of 13 electrical characteristics for cy2308sc-xx commercial temperature devices parameter description test conditions min. max. unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage [7] i ol = 8 ma ( ? 1, ? 2, ? 3, ? 4) i ol = 12 ma ( ? 1h, ? 5h) 0.4 v v oh output high voltage [7] i oh = ? 8 ma ( ? 1, ? 2, ? 3, ? 4) i oh = ? 12 ma ( ? 1h, ? 5h) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 12.0 a i dd supply current unloaded outputs, 100-mhz ref, select inputs at v dd or gnd 45.0 ma 70.0 ( ? 1h, ? 5h) ma unloaded outputs, 66-mhz ref ( ? 1, ? 2, ? 3, ? 4) 32.0 ma unloaded outputs, 33-mhz ref ( ? 1, ? 2, ? 3, ? 4) 18.0 ma notes: 6. applies to both ref clock and fbk. 7. parameter is guaranteed by design and characterization. not 100% tested in production.
cy2308 document #: 38-07146 rev. *b page 5 of 13 switching characteristics for cy2308sc-xx commercial temperature devices [8] parameter name test conditions min. typ. max. unit t 1 output frequency 30-pf load, all devices 10 100 mhz t 1 output frequency 20-pf load, ? 1h, ? 5h devices [9] 10 133.3 mhz t 1 output frequency 15-pf load, ? 1, ? 2, ? 3, ? 4 devices 10 133.3 mhz duty cycle [7] = t 2 t 1 ( ? 1, ? 2, ? 3, ? 4, ? 1h, ? 5h) measured at 1.4v, f out = 66.66 mhz 30-pf load 40.0 50.0 60.0 % duty cycle [7] = t 2 t 1 ( ? 1, ? 2, ? 3, ? 4, ? 1h, ? 5h) measured at 1.4v, f out <50.0 mhz 15-pf load 45.0 50.0 55.0 % t 3 rise time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 30-pf load 2.20 ns t 3 rise time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 15-pf load 1.50 ns t 3 rise time [7] ( ? 1h, ? 5h) measured between 0.8v and 2.0v, 30-pf load 1.50 ns t 4 fall time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 30-pf load 2.20 ns t 4 fall time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 15-pf load 1.50 ns t 4 fall time [7] ( ? 1h, ? 5h) measured between 0.8v and 2.0v, 30-pf load 1.25 ns t 5 output to output skew on same bank ( ? 1, ? 2, ? 3, ? 4) [7] all outputs equally loaded 200 ps output to output skew ( ? 1h, ? 5h) all outputs equally loaded 200 ps output bank a to output bank b skew ( ? 1, ? 4, ? 5h) all outputs equally loaded 200 ps output bank a to output bank b skew ( ? 2, ? 3) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge [7] measured at v dd /2 0 250 ps t 7 device to device skew [7] measured at v dd /2 on the fbk pins of devices 0 700 ps t 8 output slew rate [7] measured between 0.8v and 2.0v on ? 1h, ? 5h device using test circuit #2 1v/ns t j cycle to cycle jitter [7] ( ? 1, ? 1h, ? 4, ? 5h) measured at 66.67 mhz, loaded outputs, 15-pf load 200 ps measured at 66.67 mhz, loaded outputs, 30-pf load 200 ps measured at 133.3 mhz, loaded outputs, 15-pf load 100 ps t j cycle to cycle jitter [7] ( ? 2, ? 3) measured at 66.67 mhz, loaded outputs 30-pf load 400 ps measured at 66.67 mhz, loaded outputs 15-pf load 400 ps t lock pll lock time [7] stable power supply, valid clocks presented on ref and fbk pins 1.0 ms notes: 8. all parameters are specified with loaded outputs. 9. cy2308 ? 5h has maximum input frequency of 133.33 mhz and maximum output of 66.67 mhz.
cy2308 document #: 38-07146 rev. *b page 6 of 13 operating conditions for cy2308si-xx industrial temperature devices parameter description min. max. unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ? 40 85 c c l load capacitance, below 100 mhz 30 pf load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance [6] 7pf t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics for cy2308si-xx industrial temperature devices parameter description test conditions min. max. unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage [7] i ol = 8 ma ( ? 1, ? 2, ? 3, ? 4) i ol = 12 ma ( ? 1h, ? 5h) 0.4 v v oh output high voltage [7] i oh = ? 8 ma ( ? 1, ? 2, ? 3, ? 4) i oh = ? 12 ma ( ? 1h, ? 5h) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 25.0 a i dd supply current unloaded outputs, 100 mhz, select inputs at v dd or gnd 45.0 ma 70( ? 1h, ? 5h) ma unloaded outputs, 66-mhz ref ( ? 1, ? 2, ? 3, ? 4) 35.0 ma unloaded outputs, 66-mhz ref ( ? 1, ? 2, ? 3, ? 4) 20.0 ma
cy2308 document #: 38-07146 rev. *b page 7 of 13 switching characteristics for cy2308si-xx industrial temperature devices [8] parameter name test conditions min. typ. max. unit t 1 output frequency 30-pf load, all devices 10 100 mhz t 1 output frequency 20-pf load, ? 1h, ? 5h devices [9] 10 133.3 mhz t 1 output frequency 15-pf load, ? 1, ? 2, ? 3, ? 4 devices 10 133.3 mhz duty cycle [7] = t 2 t 1 ( ? 1, ? 2, ? 3, ? 4, ? 1h, ? 5h) measured at 1.4v, f out = 66.66 mhz 30-pf load 40.0 50.0 60.0 % duty cycle [7] = t 2 t 1 ( ? 1, ? 2, ? 3, ? 4, ? 1h, ? 5h) measured at 1.4v, f out <50.0 mhz 15-pf load 45.0 50.0 55.0 % t 3 rise time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 30-pf load 2.50 ns t 3 rise time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 15-pf load 1.50 ns t 3 rise time [7] ( ? 1h, ? 5h) measured between 0.8v and 2.0v, 30-pf load 1.50 ns t 4 fall time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 30-pf load 2.50 ns t 4 fall time [7] ( ? 1, ? 2, ? 3, ? 4) measured between 0.8v and 2.0v, 15-pf load 1.50 ns t 4 fall time [7] ( ? 1h, ? 5h) measured between 0.8v and 2.0v, 30-pf load 1.25 ns t 5 output to output skew on same bank ( ? 1, ? 2, ? 3, ? 4) [7] all outputs equally loaded 200 ps output to output skew ( ? 1h, ? 5h) all outputs equally loaded 200 ps output bank a to output bank b skew ( ? 1, ? 4, ? 5h) all outputs equally loaded 200 ps output bank a to output bank b skew ( ? 2, ? 3) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge [7] measured at v dd /2 0 250 ps t 7 device to device skew [7] measured at v dd /2 on the fbk pins of devices 0 700 ps t 8 output slew rate [7] measured between 0.8v and 2.0v on ? 1h, ? 5h device using test circuit # 2 1v/ns t j cycle to cycle jitter [7] ( ? 1, ? 1h, ? 4, ? 5h) measured at 66.67 mhz, loaded outputs, 15-pf load 200 ps measured at 66.67 mhz, loaded outputs, 30-pf load 200 ps measured at 133.3 mhz, loaded outputs, 15 pf load 100 ps t j cycle to cycle jitter [7] ( ? 2, ? 3) measured at 66.67 mhz, loaded outputs 30-pf load 400 ps measured at 66.67 mhz, loaded outputs 15-pf load 400 ps t lock pll lock time [7] stable power supply, valid clocks present- ed on ref and fbk pins 1.0 ms
cy2308 document #: 38-07146 rev. *b page 8 of 13 switching waveforms duty cycle timing t 1 t 2 1.4v 1.4v 1.4v all outputs rise/fall time output t 3 3.3v 0v 0.8v 2.0v 2.0v 0.8v t 4 output-output skew 1.4v t 5 output output 1.4v input-output propagation delay v dd /2 t 6 input fbk v dd /2 v dd /2 v dd /2 t 7 fbk, device 1 fbk, device 2 device-device skew
cy2308 document #: 38-07146 rev. *b page 9 of 13 typical duty cycle [10] and i dd trends [11] for cy2308 ? 1,2,3,4 notes: 10. duty cycle is taken from typical chip measured at 1.4v. 11. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = # of outputs; c = capacitance load per output (f); v = voltage supply (v); f = frequency (hz)) duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (% ) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (f or 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 02468 # of loaded outputs 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 02468 # of l oaded out put s 33 mhz 66 mhz 100 mhz
cy2308 document #: 38-07146 rev. *b page 10 of 13 typical duty cycle [10] and i dd trends [11] for cy2308 ? 1h, 5h duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (f or 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 02468 # of l oaded out put s 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (f or 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 02 468 # of l oaded out put s 33 mhz 66 mhz 100 mhz
cy2308 document #: 38-07146 rev. *b page 11 of 13 test circuits ordering information ordering code package name package type operating range cy2308sc ? 1 s16 16-pin 150-mil soic commercial cy2308si ? 1 s16 16-pin 150-mil soic industrial cy2308sc ? 1h s16 16-pin 150-mil soic commercial cy2308si ? 1h s16 16-pin 150-mil soic industrial cy2308zc ? 1h z16 16-pin 150-mil tssop commercial cy2308zi ? 1h z16 16-pin 150-mil tssop industrial cy2308sc ? 2 s16 16-pin 150-mil soic commercial cy2308si ? 2 s16 16-pin 150-mil soic industrial cy2308sc ? 3 s16 16-pin 150-mil soic commercial cy2308si ? 3 s16 16-pin 150-mil soic industrial cy2308sc ? 4 s16 16-pin 150-mil soic commercial cy2308si ? 4 s16 16-pin 150-mil soic industrial cy2308sc ? 5h s16 16-pin 150-mil soic commercial cy2308si ? 5h s16 16-pin 150-mil soic industrial cy2308zc ? 5h z16 16-pin 150-mil tssop commercial cy2308zi ? 5h z16 16-pin 150-mil tssop industrial 0.1 f v dd 0.1 f v dd clk out c load outputs gnd gnd test circuit # 1 v dd 0.1 f v dd clk out 10 pf outputs gnd gnd 1 k ? 1 k ? 0.1 f test circuit for t 8 , output slew rate on ? 1h, ? 5 device test circuit for all parameters except t 8 test circuit # 2
cy2308 document #: 38-07146 rev. *b page 12 of 13 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams 16-lead (150-mil) molded soic s16 51-85068-*a 16-lead thin shrunk small outline package (4.40 mm body) z16 51-85091-**
cy2308 document #: 38-07146 rev. *b page 13 of 13 document history page document title: cy2308 3.3v zero delay buffer document number: 38-07146 rev. ecn no. issue date orig. of change description of change ** 110255 12/17/01 szv change from spec number: 38-00528 to 38-07146 *a 118722 10/31/02 rgl added note 1 in page 2. *b 121832 12/14/02 rbi power up requirements added to operating conditions information

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